OREANDA-NEWS. March 17, 2016. Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it is expanding its collaboration with TSMC on an integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. The flow integrates IC-level with package design tools to provide a seamless flow with enhanced features for InFO technology, reducing overall design turnaround time. TSMC’s InFO technology can enable much more tightly coupled co-design and co-validation, simplifying heterogeneous integration of multiple dies.

Under the expanded collaboration, the companies are working together on the InFO design flow which includes the following Cadence® implementation, signoff and electrical/thermal tools:

  • Physical Verification System: Includes advanced technologies and rule decks to support design rule checking (DRC), layout versus schematic (LVS), in-design rule checking and inter-die DRC/LVS
  • Cadence System-in-Package (SiP) Layout: Supports all popular package interconnect and assembly methodologies and provides a complete constraint- and rules-driven substrate layout environment, including full 3D design visualization, verification and editing capabilities
  • Sigrity™ IC package analysis and 3D modeling: Provides a complete solution for assessment and modeling of IC packages and is comprised of industry-leading Sigrity technologies that enable signal- and Power Delivery Network (PDN)-performance assessment, 2D and 3D analysis, electrical model extraction and signoff report generation for IC packages
  • Voltus™ IC Power Integrity Solution: Cell-level power integrity tool that supports comprehensive electromigration and IR-drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy
For more information on the TSMC InFO design flow, visit: www.cadence.com/news/TSMCInFOTech.

“The InFO design flow is an example of another important collaboration between Cadence and TSMC that our customers appreciate and benefit from,” said Steve Durrill, senior product engineering group director at Cadence. “We are continuing to work together to develop the seamlessly integrated implementation and signoff InFO solution so designers can meet increasingly tight market windows as they target TSMC’s most advanced manufacturing processes.”

“The current InFO advanced wafer-level packaging technology provides cost-effective system scaling to increase system bandwidth,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We are working closely with Cadence to provide additional benefits to our joint customers with faster design turnaround time due to the smooth integration of signoff analysis tools.”