OREANDA-NEWS. Toshiba Corporation announced that it has developed the world's fastest device controller for embedded NAND flash memory modules compliant with the Universal Flash Storage (UFS) Ver.2.0 and UFS Unified Memory Extension (UME) Ver.1.0 standards defined by JEDEC Solid State Technology Association (JEDEC).

An embedded NAND flash memory module integrating the controller achieves a random read performance about 10 times faster than modules compliant with the e*MMC(tm) standard now widely used in low- to high-end mobile devices. The device controller secures a performance equivalent to that of Solid State Drives (SSDs) for personal computers in a package as small as a fingernail.

Recent advances in CPU processing power and DRAM capacity in smartphones and tablet PCs allow users to enjoy more powerful applications, including high resolution video players and feature-rich games. Such devices also require embedded NAND flash memory modules as their main non-volatile storage. Going forward, the higher performance of embedded NAND Flash compliant with the UFS standard will secure its widespread use in high-end mobile devices.

Current embedded NAND flash memory modules are increasingly unable to store all the data required to execute commands received from the host in the on-chip RAM of their device controllers, largely because of its increasing size; the device controllers have to execute multiple reads of the command data from NAND flash memory, which slows command execution. The result is growing demand for improved random read performance and a better user experience. However, it is difficult to secure anything more than incremental improvement in random read performance, because it takes 10s of microseconds to read data from NAND flash memory.

Toshiba has developed a new device controller for embedded NAND flash memory module to overcome these issues.

The new device controller stores data for executing a command received from the host in the host-side DRAM, reducing the number of read operations from NAND flash memory. This halves the time required to process a read command. The procedure by which the device controller writes data to the host-side DRAM and reads data from host-side DRAM is compliant with the UFS UME Ver.1.0 standard, published at the same time as UFS Ver.2.0.