OREANDA-NEWS. Toshiba Corporation announced that it has introduced a new structured array that makes it possible to develop and deliver samples with a short turnaround-time, and that only requires the customization of a few layers of metal mask designs.

The new array uses technology licensed from BaySand Inc. and can create rich function, high performance, low power SoCs simply by customizing only a few metal mask layers. Compatibility with FPGAs can be achieved with verified RTL design data from the FPGA and shorten the turnaround-time for sample delivery to one-fifth that of conventional ASICs, to a minimum of just 5 weeks. Samples can also be delivered with the same pin layout as the FPGA. Another plus is that reducing the number of metal mask layers wins large reductions in the cost of NRE.

The new product uses 65nm process technology, with a 40nm line-up under development. Also, products with high-speed transceivers are under development, for each process.