OREANDA-NEWS. December 7, 2011. Fujitsu Semiconductor Limited and SuVolta, Inc. today announced that they have successfully demonstrated ultra-low-voltage operation of SRAM (static random access memory) blocks down to 0.425V by integrating SuVolta’s PowerShrink™ low-power CMOS platform into Fujitsu Semiconductor’s low-power process technology. By reducing power consumption, these technologies will make possible the ultimate in “ecological” products in the near future. Technology details and results will be presented at the 2011 International Electron Devices Meeting (IEDM) being held in Washington DC, starting December 5th.

Controlling power consumption is the primary limiter of adding features to product types ranging from mobile electronics to tethered servers and networking equipment. The biggest contributor to power consumption is supply voltage. Previously, the power supply voltage of CMOS steadily reduced to approximately 1.0V at the 130nm technology node, but it has not reduced much further as technology has scaled to the 28nm node. To reduce the power supply voltage, one of the biggest obstacles is the minimum operating voltage of embedded SRAM blocks.

By combining SuVolta’s Deeply Depleted Channel™ (DDC) transistor technology – a component of the PowerShrink platform – and Fujitsu Semiconductor’s sophisticated process technology, the two companies have verified that a 576Kb SRAM can work well at approximately 0.4V by reducing CMOS transistor threshold voltage (VT) variation to half. This technology matches well with existing infrastructures including existing system-on-chip (SoC) design layouts, existing design schemes such as body bias control, and existing manufacturing tools.