OREANDA-NEWS. June 06, 2011. SuVolta, Inc. and Fujitsu Semiconductor Limited today announced that Fujitsu Semiconductor has licensed SuVolta's innovative PowerShrink™ low-power CMOS technology. Working together, the companies have verified the technology and begun joint development activities for the commercialization of the technology. Fujitsu Semiconductor will make the technology available at 65nm process technology.

SuVolta's PowerShrink™ technology enables significant supply voltage (VDD) reductions that reduce power consumption by 50 percent without sacrificing integrated circuit (IC) operating speed. Fujitsu Semiconductor plans to implement the technology in their Application Specific Standard Product (ASSP), Application Specific Integrated Circuits (ASIC), and Customer Owned Tooling (COT) products. The first commercial offering in Fujitsu Semiconductor's 65nm product families is targeted to be available in the second half of 2012.

CMOS technology is widely employed as the conventional low-power device technology. To date, reductions in power consumption have been achieved by lowering the supply voltage as well as by reducing feature sizes. However, beyond 90nm, reductions in voltage have been difficult to achieve due to an inability to reduce variation in transistor threshold voltage. For this reason, companies have pursued power consumption reduction efforts in ICs by leveraging innovations in circuit design.

SuVolta's PowerShrink™ technology reduces the impact of fluctuations in dopant distribution -- a major contributing factor in transistor threshold voltage variability -- permitting a lowering of supply voltage, which results in reduced power consumption in CMOS devices. With these enhanced device characteristics, the PowerShrink™ technology enables a 30 percent reduction in supply voltage without any speed degradation – thus enabling a 50 percent reduction in active power consumption.

Since the SuVolta PowerShrink™ technology uses the same planar CMOS structure as conventional technology, it is fully compatible with Fujitsu Semiconductor's existing fab infrastructure. Fujitsu Semiconductor expects high mass production potential for its ASSP, ASIC, and COT products.

Fujitsu Semiconductor and SuVolta are development partners for the technology at 65nm. As a result of joint development work, the companies have verified substantial reductions in threshold voltage (VT) variation and have confirmed device functionality. The companies will continue to leverage Fujitsu Semiconductor's extensive low-power device experience, cooperating closely to incorporate SuVolta's advanced technology concepts.

"Fujitsu Semiconductor continues to advance the development of high-speed and energy efficient products," said Dr. Haruyoshi Yagi, corporate senior executive vice president at Fujitsu Semiconductor Limited. "Working closely with SuVolta on the joint technology development, Fujitsu Semiconductor has produced favorable results for reducing power consumption. By combining the SuVolta technology with our mature low-power process technology, Fujitsu Semiconductor will be able to aggressively respond to customers' requests for low-power consumption in consumer products and mobile devices."

Dr. Bruce McWilliams, SuVolta president and CEO added, "Fujitsu Semiconductor has been an excellent development partner for the SuVolta PowerShrink™ technology. Together we have proven that the technology provides significantly reduced transistor threshold variability as well as circuit operation at much lower voltages, including SRAM memories operating at below 0.5 volts. We are delighted to be working with Fujitsu Semiconductor on the commercialization of the technology."

The PowerShrink™ low-power platform – announced today by SuVolta – is based on an advanced Deeply Depleted Channel™ (DDC) CMOS transistor having much lower threshold voltage variation than those in use in the industry today. In addition, the platform includes DDC-optimized circuits and design techniques for biasing and voltage scaling that further reduce threshold voltage variation and optimize voltage application.