Toshiba Corporation has developed MTJ elements for STT-MRAM non-volatile Magnetoresistive Random Access memory

OREANDA-NEWS. Toshiba Corporation has developed Magnetic Tunnel Junction (MTJ) elements for STT-MRAM non-volatile Magnetoresistive Random Access memory for 2X nm generation and beyond silicon transistors cache memory, required for future high-performance low-power-consumption computing.

The MTJ elements achieve high-speed operation below 3ns and low-power current operation of under 100uA, as demanded by cache memory applications, and are the world's first devices in the 1Xnm generation. This memory will cut power consumption below that of conventional cache memory (SRAM). Further details of this technology will be presented on 15 June (local time) at the VLSI2016 international conference in Hawaii.

Development background

In recent years, the need for higher performance and lower power consumption has been increasing in various computing devices. A particular challenge is to increase the capacity of internal volatile memory such as Static Random Access Memory (SRAM), while decreasing the power consumption required for memory cells. The growing amount of power consumed by leakage current in the memory in a major concern, driving anticipation of a change from the volatile memory now used to a non-volatile memory solution. Toshiba has worked toward this in its continuing development of "Magnetic Tunneling Junction" (MTJ) which operates a high speed and lower power.

Features of this technology

Toshiba developed 1X nm size MTJ elements by using a new, finer process technology and demonstrated for the first time in the world high-speed operation below 3ns with low current consumption of under 100uA. The company also confirmed that the technology has the data retention demanded of cache memory and exhibited excellent error rate characteristics, with 2–4ns write operations, as required by high-performance cache memory. Testing of repeated performance of 3 ns write operations that assumed typical cache memory operation exhibited error-free write rates. It is expected that the power consumption of computing devices will be reduced even further by reducing the power consumption of the cache memory.