Cadence Delivers Rapid Adoption Kits Based on 10nm Reference Flow
Also available with the RAK are Cadence offerings that increase productivity for system, subsystem and IP verification, performance optimization and software enablement. The RAK can utilize performance-leading ARM Artisan physical IP and ARM POP IP for Cortex-A73 and Mali-G71, enabling designers to meet aggressive processor power, performance and area (PPA) goals.
In support of this new processor, Cadence collaborated with ARM to:
- Optimize PPA implementation by defining a full-flow reference methodology incorporating Cadence digital and signoff solutions, including Genus™ Synthesis Solution, Innovus™ Implementation System, Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution and multiple Conformal® products
- Develop a 10nm methodology containing Cortex-A73 and Mali-G71 using the Cadence digital implementation and signoff flow
- Architect SoC power and performance using the Cadence Palladium® Z1 enterprise emulation platform; augment performance with the Cadence Interconnect Workbench for ARM CoreLink™ CCI-500 and CCI-400 based systems running stress testing on Cadence simulation, Palladium Z1 emulation and Verification IP
- Enable earlier SoC software development by integrating the Cortex-A73 Fast Models with the Palladium Z1 enterprise emulation platform; in a previous integration, ARM accelerated OS boot-up by up to 50X and software execution by up to 10X
“We collaborated closely with ARM to co-optimize our advanced digital implementation and signoff solutions and our system design and verification tools with ARM Cortex-A73 and ARM Mali-G71, and mobile customers can start creating designs today,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “We’ve thoroughly tested the RAK so that designers can adopt these new technologies with confidence, speeding time to market.”
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